1. Field of the Invention
The present invention relates to a Schottky barrier tunnel single electron transistor and a method of manufacturing the same, and more particularly, to a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that uses a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide being a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region.
2. Discussion of Related Art
In general, research on implementation of a silicon-based single electron transistor (SET) and circuit has been consistently conducted in developed countries such as the US, Europe, and Japan.
However, a structure of a single electron transistor that has been implemented up to date typically uses a barrier caused by making an artificial shape in pattern dependent oxidation (PADOX) silicon using a difference of a pattern-dependent oxidation rate.
One conventional method using the PADOX process is a method of manufacturing a single electron transistor described in “Fabrication Method for IC-Oriented Si Single-Electron Transistors”, IEEE Transactions on Electron Devices, vol. 47, No. 1, pp. 147-153, 2000/1.
However, the conventional method described above has many drawbacks in that it is difficult to manufacture, to implement a reproducible single electron transistor (SET), and to artificially adjust a design parameter for improving the characteristics. In fact, the PADOX process is difficult to manufacture, and an additional process is required since the process is different from that of a field effect transistor (MOSFET) used for a peripheral circuit.
In other words, a method of implementing a single electron transistor (SET) in silicon using the PADOX and the electrical characteristics thereof are shown, in the conventional method. Specifically, with a V-PADOX process, two single electron transistors (SET) can be manufactured at the same time in a parallel arrangement.
The single electron transistor manufactured like this shows a typical coulomb oscillation characteristic at a low temperature less than 77K. However, with the conventional art, a temperature showing a favorable characteristic of the single electron transistor (SET) is less than 77K and conductivity is less than 1 uS.
To enhance such a low current characteristic, a literal gate structure was devised that connects the single electron transistor (SET) and the field effect transistor (MOSFET) in serial to amplify a low current output from the SET to thus achieve a high voltage gain. However, this has a drawback in terms of low power consumption and small size since the MOSFET is used.